TSMC's 2nm (N2) node has been in volume production since the fourth quarter of 2025, and the industry has been quietly re-pricing the entire leading edge around it. The number that keeps showing up in supply-chain reporting is $30,000 per 300mm wafer. That figure is real, and it is the most consistent price across outlets. But it is also the least important number in the story, because it is the starting point of a calculation that compounds, not the answer.
The real question is not what a wafer costs. It is what a good, sellable die costs, and how much more expensive 2nm is than 3nm once you account for the two things that sit in the denominator of that math: yield and die count. This is where the GAA (gate-all-around) transition stops being a marketing story about "2 nanometers" and starts being a cost story with real consequences for every phone, accelerator, and server chip that will ship over the next two years.
The facts at list price
TSMC's own technology page confirms the milestone: N2 "has started volume production in 4Q25 as planned" and "features industry-leading first-generation nanosheet transistor technology," per TSMC's 2nm technology page. That is the architectural shift that matters. N2 is the first TSMC node to move from FinFET to GAA nanosheet transistors, where the gate wraps all four sides of the channel instead of three. TSMC's page also lays out the roadmap that follows: the A16 node, which pairs nanosheets with a backside power rail, "will be production-ready in 2H26," and TSMC says A16 "will provide an 8-10% speed improvement at the same Vdd, a 15-20% power reduction at the same speed, and up to 1.10X chip density" compared to N2P.
The performance case for the node itself is well documented. At its 2024 symposium, TSMC projected N2 to deliver a 10% to 15% performance boost and a 25% to 30% reduction in power consumption over the N3E process, with chip density up roughly 1.15 times, per Tom's Hardware coverage of the announcement. The N2 family is planned to include at least three variants: vanilla N2, the performance-tuned N2P, and the HPC-oriented N2X. One notable change: N2P, which was originally expected to carry a backside power delivery network, will not. TSMC pushed that technology forward to A16 and A14 instead.
On price, the reporting converges. Tom's Hardware reported an N2 wafer quote that "will exceed $30,000," roughly double the roughly $15,000 to $18,500 range for N4/N5 wafers, per the Tom's Hardware price report. Wccftech, citing a separate report, notes the gap between 2nm and 3nm is being described as only 10% to 20% rather than the 50% some earlier rumors suggested, per Wccftech's pricing analysis. There is a reason for that apparent discrepancy, and it is the crux of the whole analysis: TSMC is also raising the price of its existing 3nm nodes. In that framing, N3E is estimated at $25,000 and N3P at $27,000, which makes the $30,000 N2 wafer look like a modest step up.
The math the headline hides
Here is the part the "$30,000 wafer" framing leaves out. Cost per good die is not the wafer price divided by the number of dies that fit on the wafer. It is the wafer price divided by (dies per wafer times yield). A higher wafer price and a lower early-life yield both push the result up at the same time, which is why a node-over-node wafer premium of 20% to 50% can translate into a much larger jump in the cost of a finished chip.
Let me work it with a concrete, labeled assumption. Take a mobile SoC die of about 100 square millimeters. On a 300mm wafer, that fits roughly 660 dies. At the 1.15x density gain, the equivalent N2 die shrinks to about 87 square millimeters and fits roughly 762 dies per wafer. That is a 15% increase in die count, which is exactly the density figure TSMC quoted.
Now the arithmetic. At 100% yield, a $19,000 N3 wafer yields a die of about $29, and a $30,000 N2 wafer yields a die of about $39. So even with perfect yield, the N2 die is about 37% more expensive. That is the floor.
Now add yield, which is the part that is genuinely uncertain and where I have to flag an assumption, because TSMC does not publish node-level yield figures. A mature 3nm node is typically assumed to run at high 80s to low 90s percent. A first-generation GAA node in its first year is plausibly lower. If I assume 90% for N3 and 70% for N2 (an assumption, not a sourced figure), the cost of a good die rises to about $32 on N3 and about $56 on N2. That is a premium of roughly 76%, not 37%, and not the 10% to 20% the headline framing implies.
The takeaway is that the 1.15x density gain barely offsets the wafer price increase, and early GAA yield erodes whatever small advantage there was. The "2nm is only 10% to 20% more expensive than 3nm" line is only true if you hold yield constant and compare against a 3nm wafer that TSMC has itself re-priced upward. Strip both of those conveniences away and the per-good-die premium (roughly 76% in the worked example) ends up larger than the ~58% wafer premium itself, because first-year GAA yield erodes the density advantage.
There is one more number that bears on this, and it is the single most expensive line item in the whole transition. Tom's Hardware reported that developing a single 2nm chip platform now runs to roughly $725 million, a figure that covers the full family of chips built on that platform rather than one part, as Tech Insider's pricing breakdown also notes. Amortize that across volume and the picture sharpens. Spread over one million units it is $725 per unit. Over five million it is $145. Over ten million it is $72.50. That is the hidden tax on any customer that is not Apple-scale, and it is why the node is effectively a two-tier market: the giants absorb the platform cost, and everyone else pays it into their bill of materials.
What the pitch leaves out
The demand side is the other half of the story, and it is what keeps the price where it is. TSMC's own Q2 2026 revenue breakdown, as reported, shows 2nm still at only about 3% of wafer revenue, with the 5nm family at 33% and the 3nm family at 30%. So N2 is a real but still small slice of the business, and the 3nm and 5nm nodes are still where the money is. That is not a sign of weak demand. It is a sign of a node that is still ramping, and a ramp is exactly when pricing power is strongest.
The competitive pressure is real but, on the numbers available, not yet a threat to the premium. Samsung's SF2 process reportedly reached 55% to 60% yields into early 2026, which is respectable but still below where a mature TSMC node sits, and it has not converted into confirmed major fabless wins. Japan's Rapidus has been reported to target around $20,000 per wafer for its 2nm-class process with commercial production aimed at 2027, a price that would undercut TSMC by a third, but it has no confirmed major customer yet. In other words, the cheaper alternatives exist on paper, but none of them has a proven yield track record or a proven customer base. That is the moat.
The one thing worth connecting to our other reporting: this is the same supply-chain logic behind the move to diversify fabrication away from a single foundry. When OpenAI confirmed Samsung would manufacture its next custom chip, it was doing exactly what the 2nm pricing structure incentivizes. You either pay TSMC's leading-edge premium, or you take a second source at a slightly lower yield and a slightly lower price. The 2nm cost curve is what makes that second-source bet rational.
Our read
The honest summary is that the GAA transition is real, but it is more expensive than the headline wafer price suggests, and the gap is structural rather than temporary. The 1.15x density gain is not enough to offset a wafer price that is up roughly 50% to 60% over the outgoing 3nm node, and first-year GAA yield makes the per-good-die cost even steeper. The "10% to 20% more expensive" framing is only true under the most favorable assumptions, and it quietly depends on TSMC re-pricing its own 3nm nodes upward.
For the customers, this means 2nm is a premium tier, not a default. Apple and a handful of AI accelerator designers can absorb the $725 million platform cost and the per-die premium. For everyone else, the rational move is to stay on 3nm or 5nm for as long as the performance-per-watt gap does not force a move, or to take a second-source bet at a lower yield. The node will ramp, yields will improve, and the premium will narrow over time. But for the next two years, the cost of "2 nanometers" is a real and measurable number, and it is sitting in the bill of materials of every flagship device that ships.